ARRIS-D5-QAM-POST-MIB
The ARRIS-D5-QAM-POST-MIB facilitates the monitoring and management of manufacturing-specific QAM modulation parameters and signal integrity metrics on Arris D5 Universal Edge QAM (UEQ) hardware. This module provides access to counters and gauges essential for validating post-modulation signal performance during device production and factory acceptance testing.
Imported Objects
Objects
31 total| Object Name |
|---|
d5QamPOSTMibArris D5 UEQ QAM Manufacturing MIB MODULE-IDENTITY .1.3.6.1.4.1.4115.1.8.1.5.2 |
d5QamMemoryTestTableThis table contains a list of QAM POST tests and test-results for
each of the memory banks SEQUENCE OF D5QamMemoryTestEntry .1.3.6.1.4.1.4115.1.8.1.5.2.1 |
d5QamMemoryTestEntryAn entry for a single memory bank POST test and result. D5QamMemoryTestEntry .1.3.6.1.4.1.4115.1.8.1.5.2.1.1 |
d5QamMemoryTestSlotIdQAM card associated with a particular test. Unsigned32 .1.3.6.1.4.1.4115.1.8.1.5.2.1.1.1 |
d5QamMemoryTestBankIdA unique identifier specifying a particular memory bank. Unsigned32 .1.3.6.1.4.1.4115.1.8.1.5.2.1.1.2 |
d5QamMemoryTestDescriptionA textual description of the the memory bank.ro DisplayString (SNMPv2-TC) .1.3.6.1.4.1.4115.1.8.1.5.2.1.1.3 |
d5QamMemoryTestChipSelect a particular chip for a DVT test, this field
is ignored for all other testsrw Enumeration .1.3.6.1.4.1.4115.1.8.1.5.2.1.1.4 |
d5QamMemoryTestExecuteControl for starting a test and checking for test completion.
Only a value of stop or startXXX is allowed on write access.
Only a value of idle or running is allowed on read access.rw Enumeration .1.3.6.1.4.1.4115.1.8.1.5.2.1.1.5 |
d5QamMemoryTestResultVectorLast test result vector, its interpretation is test specificro Unsigned32 .1.3.6.1.4.1.4115.1.8.1.5.2.1.1.6 |
d5QamMemoryTestResultRegisterLast test result register, its interpretation is test specificro Unsigned32 .1.3.6.1.4.1.4115.1.8.1.5.2.1.1.7 |
d5QamMemoryTestResultAddressLast test result address, its interpretation is test specificro Unsigned32 .1.3.6.1.4.1.4115.1.8.1.5.2.1.1.8 |
d5QamRS232TableThis table allow access to RS232 bus of available QAM cards SEQUENCE OF D5QamRS232Entry .1.3.6.1.4.1.4115.1.8.1.5.2.2 |
d5QamRS232EntryAn entry for a single QAM card RS232 bus. D5QamRS232Entry .1.3.6.1.4.1.4115.1.8.1.5.2.2.1 |
d5QamRS232SlotIdSlot associated with a particular QAM card. Unsigned32 .1.3.6.1.4.1.4115.1.8.1.5.2.2.1.1 |
d5QamRS232StatusRetrieve the status of the RS232 bus as documented in
D5 Mux & PHY FPGAs Firmware Interface Specification section [2.4.14]ro Unsigned32 .1.3.6.1.4.1.4115.1.8.1.5.2.2.1.2 |
d5QamRS232DataOn writing, the octet string is pushed to the RS232 transmit FIFO
and flushed to the QAM micro-controller.
On reading, the octet string contains the content of the RS232
receive FIFO.rw OCTET STRING .1.3.6.1.4.1.4115.1.8.1.5.2.2.1.3 |
d5QamECLTableThis table allow access to ECL bus of available QAM cards SEQUENCE OF D5QamECLEntry .1.3.6.1.4.1.4115.1.8.1.5.2.3 |
d5QamECLEntryAn entry for a single QAM card ECL bus. D5QamECLEntry .1.3.6.1.4.1.4115.1.8.1.5.2.3.1 |
d5QamECLSlotIdSlot associated with a particular QAM card. Unsigned32 .1.3.6.1.4.1.4115.1.8.1.5.2.3.1.1 |
d5QamECLAddressthe ECL address for the transactionrw Unsigned32 .1.3.6.1.4.1.4115.1.8.1.5.2.3.1.2 |
d5QamECLValueThe ECL value for the write transaction, or the result of a
Read transaction.rw Unsigned32 .1.3.6.1.4.1.4115.1.8.1.5.2.3.1.3 |
d5QamECLExecuteControl for an ECL transaction.
Only a value of read or write is allowed on write access.
Only a value of idle, running or fail is allowed on read access.rw Enumeration .1.3.6.1.4.1.4115.1.8.1.5.2.3.1.4 |
d5QamConfigurationControlTableThis table allow controlling internal aspects of QAM card configuration SEQUENCE OF D5QamConfigurationControlEntry .1.3.6.1.4.1.4115.1.8.1.5.2.4 |
d5QamConfigurationControlEntryAn entry for a single QAM card configuration. D5QamConfigurationControlEntry .1.3.6.1.4.1.4115.1.8.1.5.2.4.1 |
d5QamConfigurationControlSlotIdSlot associated with a particular QAM card. Unsigned32 .1.3.6.1.4.1.4115.1.8.1.5.2.4.1.1 |
d5QamConfigurationControlResetNowSetting this object to true(1) causes the device to reset.
Reading this object always returns false(2).rw TruthValue (SNMPv2-TC) .1.3.6.1.4.1.4115.1.8.1.5.2.4.1.2 |
d5QamConfigurationControlManufacturingTestsEnable/disable manufacturing tests.rw TruthValue (SNMPv2-TC) .1.3.6.1.4.1.4115.1.8.1.5.2.4.1.3 |
d5QamConfigurationControlPreDistortionCoefsEnable/disable pre-distortion coefficients usage.rw TruthValue (SNMPv2-TC) .1.3.6.1.4.1.4115.1.8.1.5.2.4.1.4 |
d5QamPOSTConformance OBJECT IDENTIFIER .1.3.6.1.4.1.4115.1.8.1.5.2.99 |
d5QamPOSTGroups OBJECT IDENTIFIER .1.3.6.1.4.1.4115.1.8.1.5.2.99.1 |
d5QamPOSTCompliances OBJECT IDENTIFIER .1.3.6.1.4.1.4115.1.8.1.5.2.99.2 |
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