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USR-CHIPSET-MIB

Detailed view of the defined objects, syntax rules, and hierarchical paths.

12
Objects
Active
Status
2
Dependencies

Imported Objects

Objects

12 total
Object Name
IMPORTSThis setting determines how interleaving is configured for the ADI 918 chipset (bit 20 of Utopia register).rw
Enumeration
.1.3.6.1.4.1.429.4.33.1
adiOptionsSettingsThis value is written to the OPTN.options register of the 910/918 chipset.rw
INTEGER
.1.3.6.1.4.1.429.4.33.2
adiPSDMSettingsSetting for the PSDM.config register.rw
INTEGER
.1.3.6.1.4.1.429.4.33.3
adiActualPSDMSettingsSetting for the PSDM.actual register.ro
INTEGER
.1.3.6.1.4.1.429.4.33.4
adiGLiteFlagThis setting controls what Standards we are in, G. Lite or full rate T1.413, G.Dmt, or Multimode modes .rw
Enumeration
.1.3.6.1.4.1.429.4.33.5
adiManualRetrainForce manual retrain in G-Lite moderw
INTEGER
.1.3.6.1.4.1.429.4.33.6
adiClearProfilesClear profiles in G-Lite moderw
INTEGER
.1.3.6.1.4.1.429.4.33.7
adiUtopiaSettingThis value is written to the Utopia register of the 918 chipset.rw
INTEGER
.1.3.6.1.4.1.429.4.33.8
adiEocFlagThis flag controls whether or not EOC processing is enabled.rw
INTEGER
.1.3.6.1.4.1.429.4.33.9
adiPFCL1SettingsThis value is written to the PFCL 1 register of the 910/918 chipset.rw
INTEGER
.1.3.6.1.4.1.429.4.33.10
adiOPT4SettingsThis value is written to the OPTN 4 register of the 918 chipset.rw
INTEGER
.1.3.6.1.4.1.429.4.33.11
adiOPT5SettingsThis value is written to the OPTN 5 register of the 918 chipset.rw
INTEGER
.1.3.6.1.4.1.429.4.33.12
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