APPIAN-LPORT-HDLC-MIB
AI MIB Summary
The APPIAN-LPORT-HDLC-MIB module enables the monitoring and configuration of High-Level Data Link Control (HDLC) interfaces on Appian Communications hardware, specifically tracking link status, error counters, and frame statistics for serial WAN connections.
Appian Communications HDLC Configuration and Statistics MIB.
Main OID:
acLogicalHdlc.1.3.6.1.4.1.2785.2.4.4
20
Objects
Active
Status
3
Dependencies
Imported Objects
Objects
20 total| Object Name |
|---|
acLogicalHdlcAppian Communications HDLC Configuration and Statistics MIB. MODULE-IDENTITY .1.3.6.1.4.1.2785.2.4.4 |
acLogicalHdlcTableA table containing the statistics parameters for HDLC data streams on the SONET board. The index key used is type.channel. SEQUENCE OF AcLogicalHdlcEntry .1.3.6.1.4.1.2785.2.4.4.1 |
acLogicalHdlcEntryA row in the HDLC table containing all HDLC level statistics and configuration for a specific HDLC data stream on the SONET board. AcLogicalHdlcEntry .1.3.6.1.4.1.2785.2.4.4.1.1 |
acLogicalHdlcNodeIdThe node id is the id for this specific node in the OSAP ring.ro AcNodeId (APPIAN-SMI-MIB) .1.3.6.1.4.1.2785.2.4.4.1.1.1 |
acLogicalHdlcSlotThe slot number within the chassis where the stats reside.ro AcSlotNumber (APPIAN-SMI-MIB) .1.3.6.1.4.1.2785.2.4.4.1.1.2 |
acLogicalHdlcTypeThe type of data stream that this hdlc channel is framing. The current options are DS1, DS3, or DCC.ro Enumeration .1.3.6.1.4.1.2785.2.4.4.1.1.3 |
acLogicalHdlcIndexThe acLogicalHdlcIndex is the index for this table for the specified type. For DS1 and DS3, the index is the same as the index in the timeslot table that this entity corresponds. For the case of Appian DCC, the index simply a number from 1-4.ro INTEGER .1.3.6.1.4.1.2785.2.4.4.1.1.4 |
acLogicalHdlcStatsResetSetting this attribute to True(1) will force all statistics for this row to be cleared and set to zero (0) values. Used for debugging, clearing statistics can trouble with trending and long term statistics collection by AppianVista or 3rd party trending tools.rw TruthValue (SNMPv2-TC) .1.3.6.1.4.1.2785.2.4.4.1.1.5 |
acLogicalHdlcRxFifoOverrunThe total number of receive FIFO overruns that occurred in the hdlc controller for this specified channel number. This error occurs when attemps are made to write data to a channel which is already full.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.6 |
acLogicalHdlcRxMaxPktLenViolationThe total number of receive max packet packet length violations that occurred in the hdcl controller for the specified channel number. This error occurs when an hdlc packet is received that is greater than the maximum packet length which is programmed to be 2048 bytes.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.7 |
acLogicalHdlcRxFCSErrorThe total number of receive FCS errors that occurred in the hdlc controller for this specified channel number. The FCS error is generated when the FCS from HDLC packet receieved differs from the FCS that is computed by the HDLC controller.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.8 |
acLogicalHdlcRxNonOctetAlignedThe total number of receive non-octet aligned errors that occurred in the hdlc controller for this specified channel number. This error occurs when the receieved data stream is not octet aligned.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.9 |
acLogicalHdlcRxHdlcPktAbortThe total number of receive hdlc abort errors that occurred in the hdlc controller for this specified channel number. This error occurs when and abort code (at least 7 contiguous 1's) is received.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.10 |
acLogicalHdlcRxBufferStarvationThe total number of receive buffer starvation errors that occurred in the hdlc controller for this specified channel number.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.11 |
acLogicalHdlcTxFifoUnderrunThe total number of transmit FIFO underrun errors that occurred in the hdlc controller for this specified channel number. This error occurs when attempts are made to read data from a channel that does not have any data ready to send.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.12 |
acLogicalHdlcRxBundleDiscardDupSeqThe total number of receive bundle discard duplicate sequence errors that occurred in the hdlc controller for this specified channel number.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.13 |
acLogicalHdlcRxBundleDiscardMissSeqThe total number of receive bundle discard missed sequence errors that occurred in the hdlc controller for this specified channel number.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.14 |
acLogicalHdlcRxBundleDiscardQDepthThe total number of receive bundle discard queue depth errors that occurred in the hdlc controller for this specified channel number.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.15 |
acLogicalHdlcIngressRxFramesThe total number of ingress receive frames that the MLC has received from the hdlc controller for this specified channel number.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.16 |
acLogicalHdlcEgressTxFramesThe total number of egress transmit frames that the MLC has transmitted to the hdlc controller for this specified channel number.ro Counter64 .1.3.6.1.4.1.2785.2.4.4.1.1.17 |