HPNSAPCI-MIB
AI MIB Summary
Standard SNMP MIB module defining data structures for HPNSAPCI-MIB.
43
Objects
Active
Status
3
Dependencies
Imported Objects
Objects
43 total| Object Name |
|---|
hp OBJECT IDENTIFIER .1.3.6.1.4.1.11 |
RFC1213-MIB Unknown .1.3.6.1.4.1.11 |
nm OBJECT IDENTIFIER .1.3.6.1.4.1.11.2 |
hpnsa OBJECT IDENTIFIER .1.3.6.1.4.1.11.2.23 |
hpnsaPci OBJECT IDENTIFIER .1.3.6.1.4.1.11.2.23.10 |
hpnsaPciMibRev OBJECT IDENTIFIER .1.3.6.1.4.1.11.2.23.10.1 |
hpnsaPciMibRevMajorThe major revision level of the MIB.ro INTEGER .1.3.6.1.4.1.11.2.23.10.1.1 |
hpnsaPciMibRevMinorThe minor revision level of the MIB.ro INTEGER .1.3.6.1.4.1.11.2.23.10.1.2 |
hpnsaPciAgent OBJECT IDENTIFIER .1.3.6.1.4.1.11.2.23.10.2 |
hpnsaPciAgentTableA table of SNMP agents that satisfy requests for this MIB. SEQUENCE OF HPnsaPciAgentEntry .1.3.6.1.4.1.11.2.23.10.2.1 |
hpnsaPciAgentEntryA description of the agent/agents that access PCI information. HPnsaPciAgentEntry .1.3.6.1.4.1.11.2.23.10.2.1.1 |
hpnsaPciAgentIndexA unique index for this agent.ro INTEGER .1.3.6.1.4.1.11.2.23.10.2.1.1.1 |
hpnsaPciAgentNameName of the agent/agents satisfying SNMP requests for this MIB.ro DisplayString .1.3.6.1.4.1.11.2.23.10.2.1.1.2 |
hpnsaPciAgentVersionVersion number of the agent/agents satisfying SNMP requests for
this MIB.ro DisplayString .1.3.6.1.4.1.11.2.23.10.2.1.1.3 |
hpnsaPciAgentDateThe date on which this agent was created.
field octets contents range
_________________________________________________
1 1 years since 1900 0..255
2 2 month 1..12
3 3 day 1..31
4 4 hour 0..23
5 5 minute 0..59
6 6 second 0..59ro OCTET STRING .1.3.6.1.4.1.11.2.23.10.2.1.1.4 |
hpnsaPciBios OBJECT IDENTIFIER .1.3.6.1.4.1.11.2.23.10.3 |
hpnsaPciBiosPresentIdentifies whether PCI BIOS is present.
0 = not present, 1 = PCI BIOS present.ro Enumeration .1.3.6.1.4.1.11.2.23.10.3.1 |
hpnsaPciBiosVersionThe PCI BIOS version number:
low byte = minor version, high byte = major version.ro INTEGER .1.3.6.1.4.1.11.2.23.10.3.2 |
hpnsaPciBusesNumber of PCI buses in the systemro INTEGER .1.3.6.1.4.1.11.2.23.10.3.3 |
hpnsaPciConfig OBJECT IDENTIFIER .1.3.6.1.4.1.11.2.23.10.4 |
hpnsaPciTableA list of PCI device/functions entries. SEQUENCE OF HpnsaPciEntry .1.3.6.1.4.1.11.2.23.10.4.1 |
hpnsaPciEntryA description of an PCI device/function. HpnsaPciEntry .1.3.6.1.4.1.11.2.23.10.4.1.1 |
hpnsaPciBusIndexThe PCI Bus number that this entry describes.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.1 |
hpnsaPciDeviceIndexThe PCI device or slot number that this entry describes.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.2 |
hpnsaPciFunctionIndexThe PCI function that this entry describes.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.3 |
hpnsaPciVendorIdIdentifies the manufacturer of the device. 0xFFFF is an
invalid value for a vendor ID.
Vendor ID Manufacturer
-
XXXX Hewlett-Packard Co.ro Enumeration .1.3.6.1.4.1.11.2.23.10.4.1.1.4 |
hpnsaPciDeviceIdIdentifies the particular device. This identier is allocated
by the vendor.
Device ID Description
-
XXXX Blah! Blah!ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.5 |
hpnsaPciRevisionIdSpecifies a device specific revision identifier.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.6 |
hpnsaPciHeaderTypeIdendifies the layout of bytes 10h-3Fh in configuration
space and whether or not the device contains multiple
functions.
Bit 7: 1=multi-function device, 0=single function
Bit 6-0: Defines layout, 0 is only layout defined,
all other values are reserved.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.7 |
hpnsaPciClassCodeIdentifies the generic function of the device.
Base Sub- Prog
Class Class If. Meaning
- - -
00h Device built before Class Code
definitions were finalized.
00h 00h All currently implemented devices
except VGA compatible devices.
01h 00h VGA compatible device
01h Mass Storage controller
00h 00h SCSI bus controller
01h 00h IDE controller
02h 00h Floppy disk controller
03h 00h IPI bus controller
80h 00h Other mass storage controller
02h Network controller
00h 00h Ethernet controller
01h 00h Token Ring controller
02h 00h FDDI controller
80h 00h Other network controller
03h Display controller
00h 00h VGA compatible controller
01h 00h XGA controller
80h 00h Other display controller
04h Multimedia device
00h 00h Video
01h 00h Audio
80h 00h Other multimedia device
05h Memory controller
00h 00h RAM
01h 00h Flash
80h 00h Other memory controller
06h Bridge device
00h 00h Host bridge
01h 00h ISA bridge
02h 00h EISA bridge
03h 00h MC bridge
04h 00h PCI-to-PCI bridge
05h 00h PCMCIA bridge
80h 00h Other bridge device
07h-FEh Reserved
FFh Device does not fit in any
defined classes.ro OCTET STRING .1.3.6.1.4.1.11.2.23.10.4.1.1.8 |
hpnsaPciCommandProvides course control over a device's ability to generate
and respond to PCI cylces.
Bit Description
0 IO Space
1 Memory Space
2 Bus Master
3 Special Cycles
4 Memory Write and Invlaidate Enable
5 VGA Palette snoop
6 Parity Error Response
7 Wait cycle control
8 SERR# enable
9 Fast Back-to-Back Enable
10-15 Reservedro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.9 |
hpnsaPciStatusStatus information for PCI bus related events.
Bit Description
0-6 Reserved
7 Fast Back-to-Back Capable
8 Data Parity Detected
9-10 DEVSEL timing; 00=fast, 01=medium, 10=slow
11 Signal Target Abort
12 Received Target Abort
13 Received Master Abort
14 Signaled System Error
15 Detected Parity Errorro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.10 |
hpnsaPciCacheLineSizeSpecifies the system cache line size in units of 32-bit words.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.11 |
hpnsaPciLatencyTimerSpecifies, in units of PCI bus clocks, the value of the
Latency Timer for this PCI bus master.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.12 |
hpnsaPciBistThis optional register is used for control and status
of Built-in Self Test. Devices that don't support BIST
must always return a value of 0.
Bit Description
7 0=BIST not supported, 1=BIST supported
6 Wrtie a 1 to invoke BIST. Devices resets the
bit when BIST is complet. Software should fail
device if BIST is not complete after 2 seconds.
5-4 Reserved
3-0 0=Device passed test, non-zero= device-specific
failure code.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.13 |
hpnsaPciInterruptLineCommunicates interrupt line routing information. The value
in this register tells which input of the system interrupt
contoller(s) the device's interrupt pin is connected to.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.14 |
hpnsaPciInterruptPinTells which interrupt pin the device uses.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.15 |
hpnsaPciMaxLatSpecifies how often the device needs to gain access to
the PCI bus.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.16 |
hpnsaPciMinGntSpecifies how long a burst period the device needs assuming
a clock rate of 33MHz.ro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.17 |
hpnsaPciBaseAddrRegsBase address mapping registers for memory and IO. Refer
to the PCI specification for the format.ro OCTET STRING .1.3.6.1.4.1.11.2.23.10.4.1.1.18 |
hpnsaPciExpRomBaseAddr4-byte register is defined to handle the base address
and size information for an expansion ROM.
Bit Description
31-11 Expansion ROM Base Address (upper 21 bits)
10-1 Reserved
0 0 = address decoding is disabled and no access
to this space are allowed.
1 = address decoding enabled.ro OCTET STRING .1.3.6.1.4.1.11.2.23.10.4.1.1.19 |
hpnsaPciDeviceSpecificDevice specific configuration space.ro OCTET STRING .1.3.6.1.4.1.11.2.23.10.4.1.1.20 |
hpnsaPciSlotNumberThe physical PCI slot numberro INTEGER .1.3.6.1.4.1.11.2.23.10.4.1.1.21 |